M

mapped, virtual address region
mapping table
Mask, field
master state
   and flow control
matches, multiple, in TLB
memory dependencies
memory ordering
memory protection
MFC0, instruction [1] [2]
MIPS III ISA, disabled and enabled
MIPS IV, instruction set see also ISA
mispredicted branch [1] [2]
mode bits
   SCClkDiv
   SysClkDiv
   CohPrcReqTar [1] [2] [3]
   CTM [1] [2]
   ODrainSys
   PrcElmReq [1] [2]
   PrcReqMax [1] [2]
   SCBlkSize [1] [2] [3]
   SCClkDiv [1] [2]
   SCClkTap
   SCCorEn
   SCSize [1] [2]
mode definitions, DC
mode
   addressing
   addressing, encodings
      Kernel mode
      Supervisor mode
      User mode
   operating
Move from performance counter, instruction
Move from performance event specifier, instruction
move instruction (FP)
Move to performance counter, instruction
Move to performance event specifier, instruction
Move To/From the Performance Counter, instructions
MP, field
MTC0, instruction [1] [2] [3]
multiple matches, in TLB
multiplier pipeline
multiprocessor system
multiprocessor system, using dedicated external agents
multiprocessor system, using the cluster bus
multiprocessor system
   arbitration
   cluster bus
   with external agent